The present invention is, in general, related to a method and device for frequency synthesizing and, more specifically, to a method and device for synthesizing frequency using a digital approach. In particular, the present invention is related to a frequency synthesizer which can be designed at Hardware Description Language (HDL) level and synthesized for a target cell library, and it can also be integrated with other modules to become a multi-functional IP-based on-chip device.
As more applications such as multimedia, digital communication and microprocessors are adopting the system-on-chip (SOC) approach, it is necessary to provide an on-chip frequency synthesizer to meet the system requirements in those SOC applications. The key features of a frequency synthesizer, in general, include the pulling range, the lock-in time, resolution and stability. In the past, frequency synthesizers based on PLL/DPLL designs have been developed. The prior art synthesizer designs can be found in I. Novof, et al., "Fully-Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and .+-.50 ps Jitter," IEEE International Solid-State Circuits Conference, pp. 112-114, 1995, and C. K. Yang, et al., "A Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3V/5V Operation," IEEE J. Solid-State Circuits, vol. 32, no. 4, pp. 582-586, April, 1997. Very often, the prior art frequency synthesizers are designed using an analog approach. As a result, the design cycle cannot be reduced, and the final solution remains technology dependent. As VLSI technology advances, it is possible to provide a true digital frequency synthesizer to include the above-mentioned features.